FPGA-Based Hardware Cryptographic Core for AES-GCM High-Speed Encryption
Fully pipelined 128-bit AES encryption core written in Verilog achieving 1.2 Gbps throughput with zero CPU cycle consumption.
Project Overview
An ASIC/FPGA digital design project. Features fully unrolled and pipelined rounds of SubBytes, ShiftRows, MixColumns, and AddRoundKey alongside GHASH Galois field multiplication, providing authenticated high-speed encryption for secure optical network switches.
An ASIC/FPGA digital design project. Features fully unrolled and pipelined rounds of SubBytes, ShiftRows, MixColumns, and AddRoundKey alongside GHASH Galois field multiplication, providing authenticated high-speed encryption for secure optical network switches.
Fully pipelined 128-bit AES encryption core written in Verilog achieving 1.2 Gbps throughput with zero CPU cycle consumption.
Core Project Objectives
Capture continuous analog/digital sensor readings with robust noise filtering and hardware calibration.