FPGA-Based Hardware Cryptographic Core for AES-GCM High-Speed Encryption
Fully pipelined 128-bit AES encryption core written in Verilog achieving 1.2 Gbps throughput with zero CPU cycle consumption.
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Project Technical Overview
An ASIC/FPGA digital design project. Features fully unrolled and pipelined rounds of SubBytes, ShiftRows, MixColumns, and AddRoundKey alongside GHASH Galois field multiplication, providing authenticated high-speed encryption for secure optical network switches.
Read the foundational IEEE conference research paper, citations, and algorithmic architecture for this project.